IC Packaging Engineer
Santa Clara Valley (Cupertino), California, United States
Do you like to work on groundbreaking technologies that enable amazing new products? Do you have the attention for details and love for perfection to work towards an extraordinary result? We are looking for a talented and passionate IC Packaging Engineer. You will be responsible for IC packaging development and new product introduction for custom silicon programs requiring wafer level chip scale packaging, substrate-based IC packaging, and SIP module packaging. Looking for individuals who are innovative, creative, driven, and work well within a team.
- Typically requires at least 3+ years experience in Semiconductor Packaging Design, Process and New Product Introduction. Hands-on experience a plus.
- Strong knowledge and experience in Wafer Level Packaging, IC packaging, SIP Module packaging, single die packaging and heterogeneous package integration.
- Knowledge and experience wafer level and package assembly process, materials, and equipment.
- Strong IC packaging materials background including characterization and failure analysis.
- Problem solver with strong engineering physics. Willing to tackle tough problems.
- Ability to work independently and work with multi-functional teams.
•Lead multi-functional teams and drive package integration efforts. •Work with vendors to bring IC packaging solutions from concept to mass production. •Conduct and approve packaging proposals, designs, schematics, process flows, risk assessments, technical specifications, reliability requirements, data collection, and analysis.
Education & Experience
•Bachelors required in Electrical Engineering, Mechanical Engineering, Material Science or Physics and relevant experience within technical discipline. MS or higher degree preferred.