Chip Level PD CAD Flow and Methodology Engineer

Austin, Texas, United States
Hardware

Summary

Posted: Oct 25, 2018
Role Number: 200001112
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a Chip Level PD CAD Flow and Methodology Engineer, you will develop and support the top-level place and route methodology and flow. This flow is used by multiple projects at multiple sites. You should have a strong knowledge of top level place and route flow, UPF, algorithm, scripting (TCL/Perl) and Makefiles. You will collaborate with physical design teams, CAD team, and EDA vendors in this highly visible role.

Key Qualifications

  • 10+ years experience in hierarchical ASIC P&R and flow development.
  • Experience with all aspects of ASIC PD including floorplanning, power-distribution, multi-voltage design, pad ring construction, placement, CTS, and routing.
  • Understanding of hierarchical P&R issues including top-level floorplanning, pin- assignment, clock-distribution, critical-signal handling, UPF, MVRC, hierarchical abstractions (black-box, ILM, etc.), and handling pad-ring logic/IP
  • Strong TCL/Perl/Makefile scripting knowledge as well as experience developing complex algorithms, managing, and regressing P&R flows
  • Familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies
  • Self-motivated, enthusiastic problem solver with strong interpersonal skills
  • ICC or Encounter knowledge and prior technical leadership experience is a plus

Description

- Provide innovative solutions to improve quality of physical design - Collaborate with chip design teams to implement and customize design flows that are optimal for a given chip - Provide documentation, training and new-user-support - Own the diagnosis, resolution, regression of reported problems for multiple projects/sites - Work with CAD team to integrate the flow into the larger infrastructure

Education & Experience

BS/MS EE/CS or equivalent

Additional Requirements