Digital IC Design (PHY) Engineer
Santa Clara Valley (Cupertino), California, United States
You will be part of a silicon design group responsible for digital baseband logic design in state-of-art wireless ICs.
- The ideal candidate will have 8+ years of ASIC/VLSI design experience and a track record of developing complex ASIC functions in successful products.
- Excellent logic design experience including high speed deep sub-micron design and power management/techniques for low power design.
- Experience with DSP hardware implementations including data path and control logic.
- Familiarity with design tools for simulation, debugging, synthesis and timing analysis
- Knowledge of C/C++/systemC and DSP algorithm modeling is a plus.
- Experience with backend interface, DFT and silicon debug are pluses.
▪ RTL implementation of baseband processing modules from spec to tape out. ▪ Micro-architecture design by working with architect and algorithm teams ▪ Detailed documentation of the designs ▪ Work with verification team for test plan and function coverage ▪ Design, simulation and synthesis for PPA(power/performance/area) optimizations
Education & Experience
BSEE is required. MSEE/Ph.D is preferred