Design Verification Engineer

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted: Oct 23, 2018
Role Number: 200001198
As a member of our mixed signal ASIC team, you will be responsible for verifying complex digital IP’s. You will work with the architecture and design teams to make block level specifications clear and precise. You will use the block specifications to build verification plans describing the functionality, performance, stress cases, and error conditions to be exercised in the blocks. You will own the creation of the UVM uVC's, and the integration into block and chip level environments. Then you will build the constrained random test cases to get complete functional and code coverage for your blocks. You will participate in code reviews of other blocks in the chips, offering proposals to more efficiently achieve our goal of bug free designs on the first tapeout. A variety of tools is available to you to meet this quality target, including formal verification, digital mixed signal verification with System Verilog weighted real models of the analog blocks, and analog mixed signal verification using the schematics of the analog blocks. Although the team is small, we supply silicon to most of Apple’s industry leading hardware development teams. Do you want to be a part of building the “surprise and delight” in Apple’s future products?

Key Qualifications

  • Ten or more years of experience in a digital DV role
  • Track record as a great teammate who has taken several designs from the specification phase to successful tapeout
  • Accomplished in constrained random verification techniques
  • Accomplished in using object oriented programming techniques to develop reference models using System Verilog
  • Familiarity with one or more of the common verification frameworks (e.g. UVM, VMM, OVM)
  • Experience developing protocol checkers using System Verilog Assertions
  • Familiarity with clock domain crossing design and verification techniques
  • Experience running and debugging gate level simulations
  • Experience writing scripts in Perl, Python, or TCL

Description

•Collaborate with architects in developing precise design specifications for digital control blocks in mixed signal designs. •Use design specifications to build block and chip level verification plans. •Architect block level verification environments, and assist in architecting and crafting chip and system level verification environments. •Use System Verilog and UVM to develop drivers, checkers, and reference models. •Debug regression failures. •Use functional and code coverage to track progress and gauge tapeout readiness.

Education & Experience

•Bachelor’s degree in electrical engineering or computer science; masters or higher preferred

Additional Requirements