GPU Power Integration Engineer
Austin, Texas, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. At Apple, we push our designs to the limit in order to make amazing products. We want to delight our customers with hardware that performs while delivering long battery life. As part of the mobile GPU design team, you will collaborate with Platform Architecture, Software, Design Verification, and other design teams to micro architect and deliver RTL for GPU power management. In addition, you will be responsible for integrating applicable IP from other teams to enable complete power management solutions.
- We would like you have the following skills and experience including 5+ years of industry experience
- Proven expertise in GPU, CPU, or SOC power management
- Expertize in energy-efficient/low-power logic design
- Proficient in Verilog and/or System Verilog
- Familiarity with logic simulation, debug, and scripting languages
- Experience in logic optimization, synthesis, timing analysis, floor-planning, multiple voltage domains, and asynchronous crossings
- Knowledge of computer architecture and system interconnect protocols
- Ability to work well in a team and be productive under bold schedules.
- Graphics hardware background a plus
You will be responsible for crafting micro architecture specifications Write and deliver high quality RTL Integrate IP from other teams Close performance, power, area, functionality and lint for designs▪ Review and signoff specifications for customers and IP providers Triage power management issues in pre and post silicon Collaborate effectively with IP teams spanning multiple sites Provide schedules to IP teams and management
Education & Experience
BS/MS/PhD CE, EE, CS, or related field