Analog Layout Designer
Santa Clara Valley (Cupertino), California, United States
The PMU team is looking for qualified, motivated layout engineers from a variety of skill levels. We are a fast-growing and highly diverse group. With an employee-friendly schedule, we are in charge of both all high-performance analog IPs and building complex chip levels integral to the function of Apple’s world-class products. You will become a member of a team that not only provides an environment optimal for the refinement of engineering abilities, but also promotes passion, creativity, and collaboration. Since we believe multiple perspectives and input sources are integral to innovation and invention, we highly value diversity and equal opportunities for all members. As you work with our stellar analog and digital design teams and with members of integration, CAD, and circuit- and technology- engineering, you will find our team to be a highly dynamic work environment with endless learning opportunities.
- Typically requires 8+ years experience in analog/mixed-signal layout design of SubMicron CMOS circuits. Experience in PMU and chip level layout is highly preferred.
- Experience building tight matching, low capacitance, low power analog blocks, resistors, capacitors, high voltage devices, pad IOs, ESD structures, etc.
- Proficient experience with custom and standard cell based floor planning and hierarchical layout assembly.
- Deep understanding of IR drop, RC delay, electro-migration, self-heating and cross capacitance.
- Looking for strong experience with analog and DFM practices.
- High-level proficiency in interpretation of Calibre, DRC, ERC, LVS, etc. reports.
- Knowledge of MENTOR GRAPHICS or CADENCE layout tools.
- Scripting experience in PERL or SKILL CODE is considered a plus, but not required.
- Excellent communication skills and able to work with multi-functional teams.
You will be responsible to deliver PDV clean layout, this includes the following: •Working with circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed to build complex analog layout in deep SubMicron CMOS technologies. •Recognize failure prone circuit and layout structures. •Running complete set of design verification tools available on Mega-cell level (also on chip level). •Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. •Exceeding engineering specifications and expectations by working closely with the circuit design teams. •Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
Education & Experience
•BSEE, MSEE, PhD, or equivalent