Front-End Methodology CAD Engineer - Lint/CDC/RDC/BIST & Integration

Austin, Texas, United States
Hardware

Summary

Posted: Nov 7, 2018
Role Number: 200001219
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a Front-End Methodology CAD Engineer, you will play a major role in promoting a reliable work environment for developing, maintaining and improving our Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) applications for our SoCs across multiple design sites. In addition, you will have the opportunity to write and support software and scripts that teams use to insert Memory BIST/BIRA into designs, verify those systems, and manage test patterns. As a Front-End Methodology CAD Engineer, you will play a major role in promoting a reliable work environment for Design and Design Verification (DV) teams that allow the most concurrent development of IPs and full chip integration within a SoC (system-on-chip) project. In addition to maintaining and growing this environment, you are also responsible for developing, maintaining and improving our Clock Domain Crossing (CDC) application for our SoCs across multiple design sites.

Key Qualifications

  • Typically requires at least 5+ years of relevant experience
  • Expertise in TCL and/or PERL is required
  • Experience in Verilog and System Verilog is a plus
  • Experience in Clock-Domain-Crossing (CDC) solutions and Reset-Domain-Crossing (RDC) solutions
  • Knowledge in Spyglass is a plus
  • Understanding of FE design flow
  • Familiarity with Memory BIST, DFT implementation and synthesis flows are a plus
  • Source control system management (Perforce) is a plus
  • Excellent communication skills and prior experience in supporting VLSI flows
  • High degree of comfort in co-developing an existing, integrated debug system

Description

In this highly visible role, you will be: - Responsible for developing, maintaining and enhancing our Clock Domain Crossing (CDC) application for our SoCs across multiple design sites - Responsible for developing, maintaining, and improving existing solutions for Reset Domain Crossing (RDC) flows and support the design team - Responsible for developing and maintaining an existing systems for BIST insertion and DFT structure verification. - Responsible for supporting multiple DFT and design teams. - Utilize your debugging experience to debug vendor tool problems and collaborate with designers to help solve their problems - You will work closely with EDA vendor representatives to drive improvements and new methodologies - You will participate in the automation of project creation and version control system work flows

Education & Experience

MS/BS Degree in technical discipline

Additional Requirements