Digital Mixed-Signal Verification Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200001683
A new Mixed-Signal ASIC Design Team is searching for a self-motivating, passionate engineer for the role of Digital Mixed-Signal Verification Engineer. You will become a member of a hands-on development team that cultivates engineering perfection, creativity and innovation. Collaboration across teams is a key component of success at Apple. We are a fast-growing and highly diverse group, and you will work as part of a design team that will drive the next generation of technology for Apple's mobile products.

Key Qualifications

  • Positions are available for multiple experience levels
  • Has deep understanding of event-driven simulator based modeling techniques
  • Has strong knowledge of mixed signal concepts and digital-analog interface
  • Is proficient in Verilog, SystemVerilog and Verilog-AMS hardware description languages
  • Has deep understanding of Real, wreal, EENET and user-defined-type data structures
  • Has good background in circuit design to understand transistor-level circuit schematics and analyze verification results
  • Has good grasp on scripting languages such as Perl and Python
  • Experience writing SystemVerilog assertions, checkers and knowledge of other design verification techniques a plus
  • Knowledge of data analysis tools (Matlab, Python) a plus
  • Familiarity with front-end tools (Verilog and Analog simulators, lint checkers, clock-domain crossing checkers) a plus
  • Has excellent communication skills and is able to work with multi-functional teams across different geographical locations


In this role, you will be responsible for building accurate and efficient behavioral models for analog circuits. These models will be used in SystemVerilog simulations to validate the behavior of analog circuits in the system context. You will also work closely with the architecture team to drive the feasibility and implementation of new IPs. You will collaborate with different multi-functional teams to set up AMS simulation environment and drive mixed-signal co-simulation using Verilog models of analog IP. You will participate in the design verification and silicon bring-up by performing schematic/behavioral comparisons, writing assertions, debugging code, writing analog characterization testbenches, and interacting with the analog, digital, and design verification teams.

Education & Experience

•BSEE (MSEE preferred) with 5+ years of relevant experience.

Additional Requirements