Design Verification Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200001760
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an ambitious and exceptionally talented Design Verification Engineer. As a member of our dynamic group, you will have the unique and rewarding opportunity to shape upcoming products that will delight and inspire millions of Apple’s customers every day. This role is for a DV engineer who will enable bug-free first silicon for the mixed-signal designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Key Qualifications

  • Deep knowledge of System Verilog test-bench language and UVM
  • Impactful experience developing scalable and portable test-benches
  • Significant experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
  • Deep knowledge with serial protocols such as PCIe or USB
  • Proven experience in mixed signal verification methodology for IPs such as PHYs, PLLs etc
  • In lieu of UVM knowledge, C/C++ expert level knowledge
  • Deep knowledge of one of the scripting languages: Python, Perl, TCL
  • Strong knowledge of formal verification methodology


In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches. Track and report DV progress using a variety of metrics, including bugs and coverage. Develop mixed-signal simulation environment, and work closely with analog team to ensure overall bug-free mixed-signal design.

Education & Experience

Masters Degree with 7 years or Bachelors Degree with 10 years

Additional Requirements