Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables.
- Thorough knowledge of the ASIC design timing closure flow and methodology.
- At least 3+ years’ experience in ASIC timing constraints generation and timing closure. Expertise in STA tools (Primetime) and flow.
- Knowledge of timing corners/modes, process variations and signal integrity related issues.
- Hands on experience in timing/SDC constraints generation and management.
- Proficient in scripting languages (TCL and Perl).
- Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools.
- Understand and implement improving existing methodologies and flows. Experience in reducing the number of timing signoff corners by merging different timing modes is highly desired.
- Strong background in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer).
- Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing.
- Self-starter and highly motivated.
As an ASIC Integration Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation. Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications. Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.
Education & Experience
BSEE/MSEE, EECS, or CS is required