STA Engineer

Santa Clara Valley (Cupertino), California, United States


Posted: Jan 8, 2019
Role Number: 200001941
Does making the next extraordinary technology product excite you? Imagine what you could do here. We bring passion and dedication to our job and when you are a part of our team there's no telling what you could accomplish. At Apple, new ideas have a way of becoming excellent products, services, and customer experiences very quickly. In this highly visible role, you will be at the center of a SoC design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly

Key Qualifications

  • Thorough knowledge of the ASIC design timing closure flow and methodology.
  • At least 3+ years’ experience in ASIC timing constraints generation and timing closure. Expertise in STA tools (Primetime) and flow
  • Knowledge of timing corners/modes, process variations and signal integrity related issues
  • Hands on experience in timing/SDC constraints generation and management
  • Proficient in scripting languages (TCL and Perl)
  • Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools
  • Understand and implement improving existing methodologies and flows. Experience in reducing the number of timing signoff corners by merging different timing modes is highly desired.
  • Strong background in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer)
  • Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing
  • Self-starter and highly motivated


As an ASIC Integration Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation Develop and maintain methodology and flows related to timing verification and closure Generation of block and full chip timing constraints Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs

Education & Experience

BSEE/MSEE, EECS, or CS is required.

Additional Requirements