FE Methodology CAD Engineer
Austin, Texas, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a Front-End Methodology CAD Engineer, you will play a major role in promoting a reliable work environment for Design and Design Verification (DV) teams that allows the most concurrent development of IPs and fullchip integration within an SoC (system-on-chip) project. In addition to maintaining and growing this environment, you are also responsible for developing, maintaining and improving our Clock Domain Crossing (CDC) applications for our SoCs across multiple design sites, Austin being your primary site. You will also have the opportunity to support other front-end flows, which includes verification solutions. You will work closely with EDA vendor representatives to drive improvements and new methodologies. You will participate in the automation of project creation and version control system work flows.
- Typically requires at least 5+ years of relevant experience
- Expertise in Verilog and System Verilog is required
- Expertise in TCL and/or PERL is required
- Experience in CDC solutions
- Knowledge in Spyglass is a plus
- Knowledge in Design Compiler is a plus
- Knowledge in simulation is a plus
- Understanding of FE design flow
- Familiarity with synthesis and DFT implementation flows is a plus
- Source control system management (Perforce) is a plus
- Excellent communication skills and prior experience in supporting VLSI flows
- Comfortable co-developing an existing, integrated debug system
Core responsibilities include: - Working as a key FE CAD liaison for RTL automation, analysis and verification flows - Responsible for developing, maintaining, and improving existing solutions across LINT, CDC, RDC analysis flows and support the design team - Assist with supporting RTL generator and BIST insertion flows - Help with supporting existing Jasper reset analysis and formal proofing flows - Identify opportunities for the development or deployment of new technologies and tools - Utilize your debugging experience to debug vendor tool problems and interact with designers to help tackle their problems.
Education & Experience
MS/BS Degree in technical discipline.