DFT Design Verification-SoC
Austin, Texas, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices Imagine what you could do here. At Apple, great ideas have a way of becoming great products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish.
- You will have DFT DV experience, leading efforts for large processor and/or SOC designs.
- Advanced knowledge of CPU & SOC architecture/design & in-depth knowledge of verification flow
- Knowledge of Verilog, System Veriog, simulators and waveform debugging tools
- Knowledge of industry standards for DFT and design tools
- Deep understanding of DV methodologies for validating DFT implementation in simulation pre-silicon
- Experience in debugging JTAG/1500 related issues
- Deep understanding in constrained random verification process, coverage analysis, assertion methodology & philosophy
- Strong coding skills required and experience with OOP is a plus
In this highly visible role, you will be at the center of a semiconductor design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly. You will review specifications, develop attributes, tests & coverage plans, define methodology & test benches. Work closely with design & micro-architecture teams to understand the functional & performance goals. Stay abreast with design specs, conduct test plan reviews, develop block/full chip tests & triage of failures. Posses strong social skills combined with good collaborative approaches to own the verification efforts in a specific area of the design. Support gate level verification, run regressions, handle bug tracking, analyze coverage, etc. You will work independently & run work you're doing to align with the project goals plus support multi-functional engineering efforts.
Education & Experience
Bachelor's or Master's in EE or CS/CE