Chip Level PD CAD Flow and Methodology Engineer
Santa Clara Valley (Cupertino), California, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. You will develop and support the top-level place and route methodology and flow. This flow is used by multiple projects at multiple sites. Strong knowledge of top-level place and route flow, UPF, algorithm, scripting (TCL/Perl) and Makefiles are a requirement. You will work with physical design teams, CAD team, and EDA vendors.
- 10+ years experience in hierarchical ASIC P&R and flow development.
- Experience with all aspects of ASIC PD including floorplanning, power-distribution, multi-voltage design, pad ring construction, placement, CTS, and routing.
- Understand hierarchical P&R issues including top-level floorplanning, pin-assignment, clock-distribution, critical-signal handling, UPF, MVRC, hierarchical abstractions (black-box, ILM, etc.), and dealing with pad-ring logic/IP.
- Strong TCL/Perl/Makefile scripting knowledge. Experience in developing complex algorithms, managing, and regressing P&R flows.
- You should be familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies.
- We are looking for a self-motivated, dedicated problem solver. Strong interpersonal/communication skills are preferred.
- ICC or Encounter knowledge and technical leadership experience is a plus.
Provide innovative solutions to improve quality of physical design. Work with chip design teams to implement and customize design flows that are optimal for a given chip. Provide documentation, training and new-user-support. Responsible for diagnosis, resolution, regression of reported problems for multiple projects/sites. Work with CAD team to integrate the flow into the larger infrastructure.
Education & Experience
BS/MS EE/CS or equivalent