PD CAD & Methodology Engineer

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted: Oct 24, 2018
Role Number: 200002801
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices — strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple products. Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you join us in crafting solutions that do not yet exist? As a member of CAD team, you will create and support innovative physical design methodology and CAD flow for advanced SOC and CPU designs. The design flow is used by multiple projects at multiple sites. Strong knowledge of place and route CAD flow, EDA tools, UPF, algorithm, scripting (TCL/Perl/Python) and Makefiles is a requirement. You will collaborate with physical design teams, CAD team, and EDA vendors. Good interpersonal skill is critical. Excellent verbal and written communication in English is required.

Key Qualifications

  • Typically requires 3+ years experience in P&R and flow development.
  • Understand various aspects of partition level PNR including floorplanning, power planning, placement, timing/power optimization, CTS, routing, UPF
  • Understanding and exposure to extraction and timing analysis flows
  • Understand hierarchical P&R issues is a key(top-level floor planning, pin-assignment, clock-distribution, UPF, power-distribution, multi-voltage design, pad ring construction, placement, optimization, and routing)
  • Strong TCL/Perl/Python/Makefile scripting knowledge. Proven track record of managing, and regressing P&R flows.
  • You should be familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies.
  • We are looking for a self-motivated, dedicated problem solver. Strong interpersonal/communication skills are a requirement.
  • Innovus or ICC knowledge is a plus.

Description

Provide innovative solutions to support and improve quality of physical design. Work with chip design teams to implement and customize design flows that are optimal for a given chip. Provide documentation, training and new-user-support. Responsible for diagnosis, resolution, regression of reported problems.

Education & Experience

BS/MS in EE/CS or equivalent.

Additional Requirements