SoC Physical Design Engineer, Timing/STA

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted: Oct 26, 2018
Role Number: 200003214
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing state of the art process technology.

Key Qualifications

  • The ideal candidate will have 3+ years of hands-on experience in STA.
  • Familiar with all aspects of timing of large high-performance SoC designs in sub-micron technologies.
  • Proficient in STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others.
  • Familiar with circuit modeling, including SPICE models and worst-case corner selection.
  • Strong programming skills with Perl, TCL.
  • Experience with large design STA and Timing Closure.
  • Familiar with ECO techniques and implementation.
  • Good communicator who can accurately describe issues and follow them through to completion.

Description

- Work with design teams to understand and debug constraints, facilitate logic changes to improve timing. - Work with Physical Design team, highlighting issues and best practices. - Help create timing ECO’s for project tapeout. - Create/maintain scripts and methodologies for analysis and runs. - Create documentation and help with guidelines/specs. - Deep analysis of timing paths to identify key issues. - Implement timing infrastructure.

Education & Experience

MSEE or equivalent is required.

Additional Requirements