SoC Physical Design Engineer - PnR
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing state of the art process technology.
- You should have physical design experience, with recent successful tapeouts in deep submicron technology.
- Knowledgeable in partition level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification.
- Strong knowledge of PD construction & analysis flows and methodology.
- Shown ability to execute to stringent schedule & die size requirements.
- Strong communication skills.
- Experienced in industry standard tools, understand their capabilities and underlying algorithms.
- Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ
Work with logic design team to understand partition architecture and drive physical aspects early in design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Timing, physical & electrical verification, driving the signoff closure for the partitions. Resolve design and flow issues related to physical design, identify potential solutions and drive execution.
Education & Experience
MSEE or equivalent is required.