ASIC Design Engineer - Memory Controller
Portland, Oregon, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming great products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Apple is building the world’s fastest highly-parallel mobile processing systems. Apple is building industry leading SOCs for a wide range of products. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase the level of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying needs such as real-time, low latency, and high-bandwidth. In this role, you will be responsible for delivering high-performance memory controller for the SOC memory subsystem.
- Core Responsibilities
- Develop memory controller micro architecture and design specifications.
- Explore architecture and feature trade-offs in system performance, area, and power.
- Implement/debug RTL of complex logic for memory controller.
- Work with SOC team for subsystem integration.
- Work with physical design team for timing and PnR closure.
- Work with power team for achieving power targets.
- Key Qualifications:
- Possess in-depth knowledge of memory system.
- Experience in micro architecture definition, RTL coding and PPA analysis.
- Knowledge of high performance DRAM controller, PHY architecture, DFI interface.
- DRAM interface calibration/training mechanisms is a plus.
- Experience in system performance characterization and optimization.
Drive new memory system architectures from DRAM up. Explore architecture and feature trade-offs in system performance, area, and power consumption. Develop memory hierarchies for high performance parallel computer architectures (system-on-a-chip SOC). Work with performance team to develop performance/power simulators, models and test suites.
Education & Experience
Bachelor's or Master's degree in CS/CE/EE