ASIC Design Engineer - Memory Controller
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming great products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Apple is building the world’s fastest highly-parallel mobile processing systems. Our high-bandwidth multi- client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will be working with a world-class memory subsystem design team delivering dram controller, cache, switch etc. You will also be directly responsible for designing and delivering a deeply high-performance memory controller design for the next generation of Apple application processor architecture.
- A proven history of technical leadership
- 3+ years of architecture research and/or development of memory or highly interconnected system architectures
- 3+ years of RTL/micro-architecture definition
- Knowledge of high performance memory subsystem, including dram controller, PHY architecture and design, DFI interface and dram interface calibration/training mechanisms and algorithms is a plus.
- Systems experience in characterizing performance, doing comparison studies, and documenting and publishing results
Drive new memory system architectures from DRAM up. Explore architecture and feature trade-offs in system performance, area, and power consumption. Develop memory hierarchies for high performance parallel computer architectures (system-on-a-chip SOC). Work with performance team to develop performance/power simulators, models and test suites.
Education & Experience
Bachelor's or Master's degree in CS/CE/EE