ASIC Design Integration Engineer

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted:
Role Number: 200003685
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables.

Key Qualifications

  • You will have strong experience in complex ASIC design and IP integration, with a focus on high performance, low area, and low power.
  • Hands-on experience in physical aware synthesis, timing closure, and clock domain crossing (CDC) is preferred
  • Skilled in low power design and power intent description
  • Knowledge in DFT and backend related processes is a plus. Also, experience in IP release.

Description

Own all aspects of front-end development for large SOC subsystem including: IP design, IP integration, integration specification, power intent, synthesis, and timing closure. Responsible for PPA analysis of memories, macros and other critical components for IP development Work closely with chip architecture, design verification, physical design, DFT, and power teams to ensure designs are delivered on time and with the highest quality Develop and maintain methodology/flows/checks for SOC design and work with the Physical Design team for floor planning and timing closure activities Incorporate proper checks of the design process.

Education & Experience

Bachelor's or Master's in EE/CS/CE

Additional Requirements