ASIC Design Integration Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200003685
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a talented engineer to join our exciting team of problem solvers.

Key Qualifications

  • The ideal candidate will have 4+ years of experience in SoC design:
  • Experience in IP integration into SoC.
  • Industry exposure to and knowledge of SoC design methodology, especially logic synthesis, static timing analysis, and logic equivalence checking.
  • Experience with system design methodologies that contain multiple clock domains.
  • Experience in clock, power management and system debug designs a plus.
  • Experience in low-power design issues, tools, and methodologies including UPF power intent specification highly desired.
  • Scripting in Python, Tcl, Perl or other language.
  • Excellent tool and CAD flow debugging skills.
  • Excellent collaboration skills
  • Outstanding written and verbal communication.


As a senior SoC Design/Integration engineer you will have responsibilities spanning all aspects of SoC: • Responsible for chip level design infrastructure. • Integrate both internal and external IPs. • Responsibility includes feasibility, micro-architecture, RTL design, front-end implementation and post-silicon system bring-up

Education & Experience

Bachelor's or Master's in EE/CS/CE

Additional Requirements