ASIC Design Integration Engineer
Santa Clara Valley (Cupertino), California, United States
Does making the next extraordinary technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming excellent products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of our team there's no telling what you could accomplish. Apple is building industry leading mobile SOCs for a variety of products. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables.
- You will have strong experience in complex ASIC design and IP integration, with a focus on high performance, low area, and low power.
- Hands-on experience in physical aware synthesis, timing closure, and clock domain crossing (CDC) is preferred
- Skilled in low power design and power intent description
- Knowledge in DFT and backend related processes is a plus. Also, experience in IP release.
Own all aspects of front-end development for large SOC subsystem including: IP design, IP integration, integration specification, power intent, synthesis, and timing closure. Responsible for PPA analysis of memories, macros and other critical components for IP development Work closely with chip architecture, design verification, physical design, DFT, and power teams to ensure designs are delivered on time and with the highest quality Develop and maintain methodology/flows/checks for SOC design and work with the Physical Design team for floor planning and timing closure activities Incorporate proper checks of the design process. Are you ready to join the team and immerse yourself in technology of the future? Apply today.
Education & Experience
Bachelor's or Master's in EE/CS/CE