ASIC Design Engineer - Cache

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted:
Role Number: 200003704
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. In this role, you will work on crafting special purpose cache and controller, which is part and parcel of the SOC memory hierarchy.

Key Qualifications

  • Possess in-depth knowledge of memory system.
  • Experience in micro-architecture definition and RTL coding, as well as PPA (performance/power/area) analysis.
  • Knowledge of high performance, coherent memory system or interconnect architectures, and DRAM controller.
  • Strong cache design background, including good understanding of different memory organizations and trade-offs.
  • Hands-on experience with multi-processor cache coherence protocols.

Description

You will participate in Cache micro architecture development from specifications found from architecture guideline and model analysis. Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team. Develop/debug RTL design of different sections of the cache controller. Work with physical design team to close timing of the same.

Education & Experience

Bachelor's or Master's in EE/CS/CE

Additional Requirements