ASIC Design Engineer - Cache
Santa Clara Valley (Cupertino), California, United States
Does making the next extraordinary technology product excite you? Imagine what you could do here. We bring passion and dedication to our job and when you are a part of our team there's no telling what you could accomplish. At Apple, new ideas have a way of becoming excellent products, services, and customer experiences very quickly. Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying, but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller, which is part and parcel of the SOC memory hierarchy
- Possess in-depth knowledge of memory system.
- Experience in micro-architecture definition and RTL coding, as well as PPA (performance/power/area) analysis.
- Knowledge of high performance, coherent memory system or interconnect architectures, and DRAM controller.
- Strong cache design background, including good understanding of different memory organizations and trade-offs.
- Knowledge of high performance
- Hands-on experience with multi-processor cache coherence protocols.
You will participate in Cache micro architecture development from specifications found from architecture guideline and model analysis. Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team. Develop/debug RTL design of different sections of the cache controller. Work with physical design team to close timing of the same.
Education & Experience
Bachelor's or Master's in EE/CS/CE