Front End Design Integration Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200003839
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a talented engineer to join our exciting team of problem solvers.

Key Qualifications

  • The ideal candidate will have a Bachelors degree in EE or CECS with 5+ years of work experience or Masters degree in EE or CECS with 3+ years work experience
  • RTL logic design or implementation experience on multi-million gate ASICs.
  • Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies.
  • Expertise in synthesis, timing analysis, and closure.
  • Experience with scripting languages like Perl or Tcl.
  • Ability to communicate effectively across all internal groups.
  • Good understanding of logic design, Clock Domain Crossings (CDC) and Reset Domain Crossings (RDC).
  • Attention to detail and desire to learn.


As an ASIC Integration Engineer, you will have responsibilities spanning various aspects of SOC design: • Write integration specifications. • Drive all front end integration activities like Synthesis, UPF, Lint, CDC, Logical Equivalence, ECO, etc. • Integrate complex IPs into the SOC. • Integrate and optimize any memories and hard macros required for the block. • Work closely with other engineers that are members of the SOC Design, SOC Design Verification, Emulation, STA, Power, and Physical Design teams.

Education & Experience

BS or MS in EE, EECS, or CS is required.

Additional Requirements