Physical Design Verification Engineer

Santa Clara Valley (Cupertino), California, United States
Not Available

Summary

Posted: Oct 30, 2018
Weekly Hours: 40
Role Number: 200004065
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.

Key Qualifications

  • 5-10 years of physical design experience, with emphasis on physical verification
  • Strong knowledge of physical verification flows and methodology
  • Deep knowledge of all aspects of ASIC physical design
  • Scripting skills to debug flow related issues and make improvements as appropriate
  • Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc
  • Real chip tapeout experience with a track record of successful signoff
  • Layout design background and experience a plus

Description

As a member of the physical design team, you will be responsible for: - Performing various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level - Working closely with the CAD/Technology teams for flow bring up and validation - Collaborating with the Implementation team during the entire chip design cycle to drive signoff closure for tapeout - Owning schedules and supporting cross-functional engineering effort - Work on padring, bump, RDL design collaborating with the package and floorplan teams

Education & Experience

BSEE or MSEE

Additional Requirements