GPU Memory Hierarchy Design Verification Engineer

Austin, Texas, United States
Hardware

Summary

Posted: Oct 26, 2018
Role Number: 200004303
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. The GPU Memory Hierarchy Design Verification Engineer will be responsible for the pre-silicon RTL verification of cache hierarchy and related units in a low power GPU design. This includes deep understanding of the micro-architectural details of these units, interactions between the units, and the connection of the uarch to the larger architectural intent of the GPU. A strong computer architecture background, experience in cache and memory subsystem verification, and a solid foundation in verification methodology will be used to close testing coverage with high confidence.

Key Qualifications

  • The ideal candidate will have relevant 3+ years of experience including:
  • Expertise with verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL; Specman experience is ideal.
  • Strength in creating software solutions utilizing object oriented programming concepts.
  • Expertise with HDL simulators and waveform viewers.
  • Experience defining coverage space, writing coverage model, analyzing results.
  • Experience working under strict schedule deadlines with the ability to manage multiple priorities.
  • Strong knowledge of computer architecture, general purpose microprocessor.
  • Experience and expertise in memory/cache sub-system micro-architecture, which could include L1, L2, L3 caches, coherent interconnects, MMUs or related blocks.
  • Experience with Perl, Shell scripting, Makefiles, TCL a plus.
  • Excellent communication skills and ability to collaborate.
  • GPU experience, especially in the memory hierarchy area, is a plus.

Description

As a GPU Memory Hierarchy Design Verification Engineer, you will be responisble for: Developing verification plans in coordination with design leads and architects. Building and maintaining verification test bench components and environments. Generating directed and constrained random tests. Running simulations and debugging design and environment issues. Crafting functional coverage points, analyze coverage, and enhance test environment to target coverage holes. Creating automated verification flows for block verification Applying knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs Working with other block and core level engineers to ensure seamless verification flow

Education & Experience

BS/MS CE or EE

Additional Requirements