DFT Design Verification Engineer

Santa Clara Valley (Cupertino), California, United States


Posted: Oct 26, 2018
Role Number: 200004449
Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. We invite you to join us, if you are an extraordinary engineer responsible for verifying advanced DFT designs for high performance Wireless SoC. In this highly visible role, you will be at the center of DFT verification effort reviewing architecture & design, creating verification plan, executing test bench implementation, and closing coverage.

Key Qualifications

  • Expertise in DFT DV techniques for complex SOCs.
  • Deep understanding of DFT designs including fault modeling, ATPG, Scan insertion, and general logic design.
  • Excellent verification skills in problem solving, constrained random testing, and debugging.
  • Experience defining coverage space and writing coverage model.
  • Experience with Tcl a plus.
  • Experience writing scripts in languages such as Perl or Python.
  • Basic knowledge of HVL methodology (UVM/OVM/VMM).
  • Experience with low-level programming of systems in C/assembly a plus.
  • Should be a team player with excellent communication skills and the desire to take on diverse challenges.


Develop DFT DV testbench, and generate directed/constrained random tests. Debug failures, manage bug tracking, and analyze coverage. Execute & debug gate level simulation. Close coverage by working with designers and creating additional necessary tests Review specifications and extract design features to be verified. Create verification plan & define coverage models. Improve methodology by discussing with CAD engineers. Assist in verification flow, and write scripts for automation of regression.

Education & Experience

Typically requires MSEE

Additional Requirements

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.