Sr. CAD Engineer – EMIR Gate Level Analysis
Santa Clara Valley (Cupertino), California, United States
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role as a core team member in our advanced CAD Group, you will enhance your career working on state of the art designs. You’ll utilize your hands on experience in power EMIR analysis to develop/define & refine the methodologies and flows for gate-level, as well as transistor level designs. The areas will include but are not limited to functional static/dynamic IR analysis, scan mode IVD analysis, package model handling, power EM analysis, SigEM, power switch modeling, design abstract and reuse for EMIR purposes, and IP/SoC level EMIR sign-off/ECO.
- We are looking for strong engineers to join our team with 5+ years of experience in EMIR field in the following areas:
- Methodology for gate-level (PnR) EMIR analysis for multiple modes, like: static and dynamic functional modes, scan modes, jitter mode, etc.
- Most of EMIR analysis will need proper modeling from hard IPs at transistor level.
- In-depth knowledge in industry leading tools, like Redhawk, Voltus, as well as Totem and VPS
- Package modeling, package and chip level co-designs
- Proficient in programming using PERL/TCL/Shell/C/C++ etc.
- Experience in physical designs, Place & Route, Floorplanning and STA is a plus
- Flow regressions experience a plus
- Power analysis experience is useful
- Experience in library characterization for EMIR is useful
- EMIR tool validation and qualification is a nice to have
Primary responsibilities include development of custom EMIR solutions; revamping/rewriting and streamlining the EMIR flow as well as assume ownership of entire flow. You will work closely with various design groups (Physical-design/integration, Circuit-design/Power/Technology) on their EMIR requirements for various post layout flows. You will also partner with vendors/foundries for tool qualification and debug.
Education & Experience
MSEE or BSEE Degree in technical discipline