Pixel IP Design Engineer - Display Implementation
Santa Clara Valley (Cupertino), California, United States
In this highly visible role, you will be at the center of a multimedia IP design effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
- The ideal candidate will have 4+ years of experience in multimedia IP/SoC design:
- Previous experience in multimedia IP design and integration.
- Industry exposure to and knowledge of ASIC/FPGA design methodology, especially logic synthesis, static timing analysis, logic equivalence checking, and working with physical design teams for floorplanning and timng closure.
- Experience with system design methodologies that contain multiple clock domains.
- Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
- Experience in low-power design issues, tools, and methodologies including UPF power intent specification highly desired.
- Experience in datapath and video-centric designs a plus.
- Excellent collaboration skills
- Outstanding written and verbal communication
As a senior IP Design engineer you will have responsibilities spanning all aspects of multimedia IP design: • Will be responsible for imaging subsystem design/integration. • Integrate and design subsystem architectures containing both internal and external IPs. • Responsibility includes feasibility, micro-architecture, RTL design, front-end implementation and post-silicon system bring-up.
Education & Experience
• BSEE / MSEE is required