SerDes Circuit Design Engineer

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted: Oct 30, 2018
Role Number: 200005249
Apple Silicon Engineering is seeking qualified SERDES designers to work on the next generation SERDES PHYs for Apple’s world-leading systems-on-chip (SOCs). You will be part of a growing analog/mixed-signal team involved in design and productization on leading-edge CMOS process technology nodes. At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and especially talented SerDes Designer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day.

Key Qualifications

  • You should have experience in high-speed serial links with expertise in the following:
  • Deep knowledge in high-speed SerDes protocols (e.g., PCIe, USB, SATA, etc.).
  • Strong knowledge of analog CMOS designs and topologies.
  • Deep experience with Tx & Rx equalization techniques and circuits.
  • Significant experience with high speed digital circuit (e.g., serializer, deserializer, counters, dividers, etc.) design, analysis and verification (e.g., STA, formal verification).
  • Deep experience in analyzing link jitter budget for high-speed serial links and creating block level requirements.
  • Strong knowledge of different CDR architectures.
  • Experience in lab testing of high-speed serial links and defining equipment needs.

Description

Ownership of analog and digital circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, clock generation and distribution, etc.). Get along with multi-functional teams to define requirements/specs (e.g., modeling, package, board, DFT, ESD, etc.). Craft block-level specifications based on link-budget, behavioral modeling, and transistor-level feasibility. Work closely with mask design to implement layout view of designs. Generation/QA of various IP Kit views/files for release to IP consumers. Defining production/bench-level testplans. Hold design reviews of blocks with peers/management to show design meets spec targets and requirements.

Education & Experience

Masters degree with 7 years experience or PhD with 5 years experience

Additional Requirements