Power UPF Methodology Engineer
Santa Clara Valley (Cupertino), California, United States
As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if needed, bringing visionary ideas to the real world. Your efforts will be groundbreaking, often literally. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Power UPF Engineers. The SoC hardware development team is looking for a Power UPF methodology engineer who will drive power implementation and verification on our mobile products and help determine next generations of UPF framework.
- We are looking for applicants with experience in ASIC design methodology and an emphasis on power definition.
- Experience in ASIC design flows and custom IP design flows.
- Knowledge of scripting languages (Tcl, Perl and make).
- Experience with UPF and/or CPF power intent formats.
- Familiar with of power analysis and optimization methods.
- Experience with Multi-voltage static checkers (VCLP or CLP or Spyglass-LP).
- Familiar with entire RTL2GDS flow (RTL sim (VCS), equivalence, synthesis, P&R, intent checking).
- Strong communication skills are a pre-requisite since you will collaborate with a lot of different groups.
Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of talented engineers. The main responsibility of this role is to support UPF implementation and verification for mobile SOCs, make current UPF flow more robust to improve the power definition and check & expand UPF methodology next generation mobile products. - Drive coverage of power intent across static and dynamic checking methodologies. - Define and settle UPF framework for new projects. - Bring up power intent checking flows on new projects. - Drive Mixed signal IP power intent verification. - Drive power intent sign-off for tape-out. - Liaison with designers and design verification team for debugging any power intent flow issues.
Education & Experience
BSEE/MSEE or Computer Science required.
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.