SoC Physical Design Engineer, PnR
San Diego, California, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be responsible for implementing complete chip design from netlist to tapeout. You will have hands on experience in physical design and large chip integration.
- We value proven ability in all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
- Experience resolving typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
- Your practical knowledge with hierarchical design approach, top-down design, budgeting, timing and physical convergence will be an asset.
- Showcase your experience on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
- Your depth of expertise with large SoC designs (>20M gates) with frequencies in excess of 1GHz utilizing state of the art technologies will serve you well.
- We would like you to join our team if you have detailed understanding of database management issues.
- From a CAD tool perspective, experience crafting Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.
- Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle. Drive best in class PD construction and optimization recipes for performance, power and Area (PPA). Collaborate to drive methodologies and “best known methods” to streamline PD work, come up with guidelines and checklists, drive execution, and track progress. Be focal point for place and route drive the work among place and route engineers, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route Manage and resolve design and flow issues related to physical design, identify potential solutions and drive execution. Are you a confident problem solver who thrives under pressure to find new, creative solutions? Are you ready to help chart the future of Apple's ecosystem? If so, we are excited to hear from you.
Education & Experience
MSEE or equivalent is required.