SoC Physical Design Engineer, PnR
San Diego, California, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be responsible for implementing complete chip design from netlist to tapeout. You will have hands on experience in physical design and large chip integration.
- You should have a minimum of 3-5 years of physical design experience, with recent successful tapeouts in deep submicron technology. - Knowledgeable in partition level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification. - Strong knowledge of PD construction & analysis flows and methodology. - Shown ability to execute to stringent schedule & die size requirements. - Strong communication skills. - Experienced in industry standard tools, understand their capabilities and underlying algorithms. - Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ
Work with logic design team to understand partition architecture and drive physical aspects early in design cycle. - Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. - Timing, physical & electrical verification, driving the signoff closure for the partitions. - Resolve design and flow issues related to physical design, identify potential solutions and drive execution.
Education & Experience
MSEE or equivalent is required.