ESD Development Engineer

Santa Clara Valley (Cupertino), California, United States


Weekly Hours: 40
Role Number:200006542
In this role, you will be part of the team that derives the custom design rules for achieving ESD and latch-up targets of ICs developed by Apple. You will design and characterize test chips, analyze the resulting data, correlate them to critical ESD design parameters, as well as contribute to ESD and latch-up rule generations. This role involves working closely with internal teams within Apple as well as external vendors.

Key Qualifications

  • Solid understanding of ESD circuit design techniques and topologies and device physics
  • Extensive hands on experience with ESD testing and characterization equipment, such as TLP, vfTLP, HBM, CDM testers
  • Experience with Si processes for high voltage, RF, and advanced ASICs
  • Familiar with using simulation tools, such as SPICE, Spectra, etc.
  • Experience with design/layout EDA tools, including Virtuoso, Calibre, Allegro, etc.
  • Scripting skills to automate data analysis using JMP, EXCEL, etc.
  • Strong initiative and ownership of responsibilities, productive, able to meet
  • deadlines
  • Excellent written and verbal communication skills


It is your responsibility to: Design ESD and latch-up test structures to characterize Si for ESD/LUP properties. Tape out ESD and latch-up test chips by working with internal and external teams. Generate characterization plans for test chips and perform related measurements. Perform data analysis and contribute to rule generations to support internal teams. Construct compact models to enable ESD simulation. Maintain and QA existing ESD LIB and responsible for ESD LIB release. Assist with ESD and latch-up related debugs.

Education & Experience

BSEE/MSEE required

Additional Requirements