Display Silicon Architect

Santa Clara Valley (Cupertino), California, United States


Posted: Nov 1, 2018
Weekly Hours: 40
Role Number: 200006590
In this highly visible role, you will be developing the next generation iPhone display drivers, defining display silicon design guidelines, working with display electrical engineers to validate silicon/module performance and qualify the ASIC’s in the system/display integration.

Key Qualifications

  • 10+ years of analog chip design experience, leading design and integration efforts for high performance and high quality designs
  • Experience crafting high performance analog to digital converter (ADC), digital to analog converter (DAC), OPAMP
  • Experience integrating whole chip
  • Knowledge of analog fundamental, rigorous process development and analytical methodology, which lead to high quality design
  • Effective written and verbal interpersonal skills
  • Proven track record in architecting ASIC’s or electrical subsystem
  • Experience in developing and manufacturing high volume products
  • Experience in vendor technical management
  • Knowledge in electronic displays, image quality, or graphics subsystem
  • Experience with STA constraints development and analysis for DFT modes and SDF simulations
  • Ability to conduct experiments during silicon debug, capturing and analyzing data; and utilize scripting to support efficient handling of ATE data


Core Responsibilities: As a Display Silicon Architect being responsible for the chip architecture and specification in a chip design, you will have responsibilities spanning all aspects of display silicon design: - Architecting the display silicon and display sub-system - Establishing display driver IC critical blocks, and providing analysis to drive design rules and guidelines - Authoring display silicon engineering requirement specification - Working with the silicon teams to perform and review simulation - Defining the roadmap for the next generation display silicon and display subsystem - Handling silicon and system level risk and performance tradeoff

Education & Experience

BSEE / MSEE is required

Additional Requirements