SoC Power Spec Engineer
Santa Clara Valley (Cupertino), California, United States
Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? Do you have a passion for crafting entirely new solutions? Do you love building without precedent? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if needed, bringing visionary ideas to the real world. Your efforts will be groundbreaking, often literally. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Power Spec Engineers. The SoC hardware development team is looking for an expert engineer to lead the implementation of low power architectures, power reduction techniques and methodologies.
- We are looking for applicants with experience in low power architecture, ASIC design implementation for low power, ASIC physical design methodology.
- Experience with low power logic implementation.
- Experience with low power architecture techniques.
- Familiarity with ASIC design flows.
- Familiarity with physical design tools for power optimization.
- Strong communication skills are a pre-requisite since you will collaborate with a lot of different groups.
Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of talented engineers. The main responsibility of this role is to own SOC power specifications, and drive multi-functional teams to improve power efficiency. - Develop new techniques for power efficiency in our products. - Guide design implementation to achieve the power targets. - Create or improve new methodologies to improve power. - Maintain power roll-up and power spec at the chip level - Understand interactions of the product at the architecture and system level. - Drive the multi-functional power estimation and optimization with architecture, design and software teams.
Education & Experience
BSEE/MSEE or Computer Science required.
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.