CSM Physical Design Lead
Santa Clara Valley (Cupertino), California, United States
Are you a leader? Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV. We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies. We are looking for a remarkable Physical Design Lead to work with a highly talented Custom Silicon team at Apple to design and develop innovative chips for the coolest products. This position focuses specifically on supporting Physical Design and related activities for the chips.
- We are looking for applicants with 10+ years of hands-on experience in Physical Design of SoCs.
- 5+ years of experience in leading physical design teams.
- Consistent track record of having taped out a number of complex chips - from gates to GDS.
- Good knowledge of digital design concepts.
- Working knowledge of front-end design methodology including basic RTL coding, synthesis methodology, timing constraints generation, multiple clock domain handling, low power techniques.
- In depth practical, hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, MCMM timing closure, routing, DFM techniques and physical verification.
- Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor or Atoptech.
- Proficient in Static Timing Analysis and the techniques used for timing closure and noise avoidance / fixing.
- Hands-on experience in Power and Signal Integrity analysis.
- Should have the ability to debug and fix LVS, DRC, Antenna, ERC issues.
- Capability to work with multi-functional teams - internal and external and to handle multiple projects concurrently with very aggressive schedules.
- Strong analytical skills with the ability to prioritize tasks and make critical decisions.
- Familiarity with the best analog layout design practices for sensitive circuits like OpAmp, matching pair, etc.
- Willingness to travel occasionally - domestic and overseas.
- Excellent verbal and written communication skills.
- One or more of the following skills will be an added plus:
- Mixed signal SoC tapeouts involving multiple instances of analog IPs.
- Experience in DFT algorithms, memory and logic bist, physical implementation, timing closure, ATPG generation.
- Low power / leakage management methodology and techniques.
- Extraction and characterization of IP elements.
- Experience of working with and leading sub-contractor design houses and silicon vendors.
Imagine yourself at the center of our hardware development effort. Where you will collaborate with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with vendors to promote efficiency in the Silicon community. We value your technical understanding of physical design principles. You will be responsible for ensuring the high quality of the chips and is expected to: - Audit vendor PD flows and methodologies for any holes and set up issues. - Suggest improvements to their methodology to optimize it to obtain the best QoR for Apple chips. - Work closely with the internal teams like systems and program management to ensure that the vendor PD implementation team is meeting the design goals. - Work closely with experts from other teams like the packaging, process etc. to resolve any issues in the project which are in an area closely related to PD. - Conduct periodic design reviews - with deep technical dives - to make sure the project is tracking to the schedule and maintaining a high quality of work. - Review all the final PD, STA, SI, Electrical analysis reports and sign-off on them for tapeout approval. - Provide post tapeout support to work on ECOs and debug, if required. - Have the tenacity to stick to the highest standards and not succumb to pressures to sign-off on anything unless 100% satisfied. - Adhere to a strict and consistent standard of operation across all vendors and projects. - Maintain a professional relationship with the vendor and yet walk the fine line to maintain the customer-vendor distance.
Education & Experience
BSEE / MSEE is required, PhD preferred.
- Some Travel Required.
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.