SoC Physical Design Engineer P&R

Austin, Texas, United States
Hardware

Summary

Posted: Nov 9, 2018
Role Number: 200006950
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be responsible for implementing complete chip design from netlist to tapeout. Please highlight your minimum 5-10 years of hands on experience in physical design and large chip integration.

Key Qualifications

  • Familiar with all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration
  • Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions
  • Familiar with hierarchical design approach, top-down design, budgeting, timing and physical convergence
  • Prior experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain
  • Strong experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz utilizing state of the art sub 45nm technologies
  • A deep understanding of database management issues will make you a great fit for the role.
  • From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required
  • Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt

Description

Collaborate with FE team to understand chip architecture and drive physical aspects early in design cycle. Work closely with the physical design team, drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress. Be focal point for place and route drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. Resolve design and flow issues related to physical design, identify potential solutions and drive execution. Are you a confident problem solver who thrives under pressure to find new, creative solutions? Are you ready to help chart the future of Apple's ecosystem? If so, we are excited to hearing from you.

Education & Experience

BS/MS CE or EE

Additional Requirements