San Diego, California, United States
Do you love creating solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, large subsystems. You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll craft and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this role, you will be responsible for all phases of front-end logic design, with the primary focus on RTL to gate-level netlist creation.
- Do you have hands on experience in front-end design synthesis and large chip integration?
- We value your expertise in advanced synthesis techniques to achieve aggressive low power, area, and timing goals.
- Your proficiency in: STA (static timing analysis), Verilog/VHDL, formal verification, lint checks will serve you well on our team.
- Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure.
- Embrace technical challenges with your natural passion to innovate.
- Ability to collaborate effectively with different functional teams and strong written/verbal communication.
Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms. Professional experience with ECO implementation, both functional and timing closure. Familiarity with simulation, debugging tools, and working closely with DV team. Experience with multi-clock and multi-power domain designs. Familiarity with DFT insertion, and multi-mode timing constraints. Previous experience working on CPUs, GPUs or DSPs desirable.
Education & Experience
MSEE or equivalent