ASIC Design Integration Engineer
Portland, Oregon, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a talented engineer to join our exciting team of problem solvers. Apple is building industry leading SOCs for a variety of products. This is fueled by our world class ASIC design and integration teams. We have top notch engineers who are responsible for leading edge IP development and coordinating across multiple SOC teams. In this role, you will work closely with cross functional SOC teams to execute design and integration tasks for the highest quality IP deliverables.
- Strong experience in complex ASIC design and IP integration, with focus on high performance, low area, and low power
- Experience in synthesis and timing closure
- Experience in clock domain crossing (CDC) analysis
- Experience in low power design and power intent description.
- Interfacing with Physical Design team for floorplanning and timing closure activities
- Knowledge in UPF, DFT and PnR processes is a plus
Drive the FE development aspects for large SOC subsystem including: IP design/integration/specification, power intent, synthesis and timing closure Work closely with Physical Design, DFT, CDC, STA, and power teams to deliver high quality design on time Own the SOC flows/checks at various stages of the FE design process Drive the IP release process
Education & Experience
BSEE / MSEE is required