RFIC Design Engineer
San Diego, California, United States
Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible? As part of our Hardware Technology Engineering group, you’ll craft sophisticated RFIC blocks/sub-systems for wireless SoC (in wireless standards such as cellular 4G/5G/mmW, WiFi/BT, etc.). You’ll work across disciplines to transform improved hardware elements into a single, integrated design. Join us, and you’ll help us innovate new wireless systems technologies that continually outperform the previous iterations. By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world. Do you want to have an impact on every single Apple product? As a Senior RFIC Engineer on this team, you will be responsible for designing RFIC blocks/sub-systems for wireless SoC (in wireless standards such as cellular 4G/5G/mmW, WiFi/BT, etc.). This position requires someone comfortable will all aspects of RFIC design, that thrives in a dynamic multi-functional organization, is not afraid to debate ideas openly, and is flexible enough to pivot on constantly evolving requirements.
- - Direct experience designing and bringing into high-volume production ZIF RF transceivers in deep sub-micron RFCMOS technology. This includes design of on-chip LNAs and PAs, PLL/VCO/LO blocks, up-conversion/down-conversion mixers, baseband filters, data converters and calibration methods associated with such high performance wireless systems and ZIF designs. Experience should also include understanding of DFT and DFM techniques for high-volume production environment.
- - Deep understanding in system specification and able to work with system architects to translate system requirement into circuit requirement at IC level; Requires strong understanding of impact of modulation type to radio architecture and requirements.
- - Familiar with various RF transceiver architectures and their trade-offs; Demonstrate the capability to work with digital design group for an optimum partition between digital and analog domain;
- - Deep understanding of fundamentals of RF CMOS implementation, and basic building blocks, including LNAs, mixers, VCOs and DCOs, LO and PAs;
- - Deep understanding of RF device modeling, including but not limited to device noise parameters, inductor modeling. Insights into packaging effects, supply isolation, high frequency ESD structures, and circuit layout techniques for optimum RF performance;
- - Requires strong knowledge of desense and able to work closely with board RF/HW/Antenna teams to optimize board/module layouts for desense mitigation. Also, has experience with desense mitigation with integrated PMUs/DSPs (i.e. substrate isolation, return loops, package isolation, frequency planning, etc).
- - Familiar with mix signal mode verification methodology (SystemVerilog, AMS, Nanotime).
- - Familiarity with EM tools (EMX, HFSS).
- - Extensive experience in Si characterization and debug.
- Work with RF and PHY systems teams to partition system requirements and optimize RF and baseband circuit performance, power, and area. - Develop novel RFIC circuits and architectures, taking designs from concept all the way to production. - Work with digital integration/verification teams to model and verify top-level radio functionality and performance during pre-silicon phase. - Work with SiPi and packaging teams to predict/simulate RF de-sense and coupling mechanisms at chip-level and board level using EM tools. - Perform detailed bring-up and characterization of radio blocks at IP level. Support system level integration and characterization of radio performance. - Participate in RFIC/analog design reviews across Apple wireless groups.
Education & Experience
BSEE is required. MSEE/Ph.D is preferred