Platform Architect: Memory Sub-system, QOS, and Fabrics
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. Do you love working on challenges that no one has solved yet? As a member of our dynamic group, you will have the unique and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Are you ready to make an impact and transform hardware technology? We are searching for an extraordinary talented engineer with 5+/- years experience to join our exciting team of problem solvers and innovators. In this role, you will be a member of a System-on-Chip (SoC) team, working with various hardware and software engineering groups to shape the architecture of Apple's future devices. The role will focus on exploration of the memory subsystem, interconnection networks, fabrics, and Quality of Service (QoS) solutions. The position calls for independent development, definition, power and performance modeling, and documentation to meet stated system requirements.
- You will have experience/skills in several of the following areas:
- Expertise with various DRAM/SRAM memories, architecture, protocols, timing, performance analysis, perf/power trade-offs, modeling, and debug.
- Quality of Service (QoS) solutions.
- Expertise with high-bandwidth and low latency interconnects and fabrics.
- Queueing theory and applications.
- CPU, GPU, and Camera/Video memory access patterns and usage of system caches.
- Interactions and data flows between the CPUs, GPUs, Camera/Video, and I/O components on modern SoCs.
- Investigating how Apps use the SoC, by running and profiling on the live silicon (e.g. smartphone).
- C/C++ modeling of SoC and workloads at different abstraction levels, for both performance and power simulation.
- Real-time system development and modeling.
- Capturing, analyzing, and validating simulation results to compare architectural design alternatives.
- Writing specification documents, in collaboration with engineers across different disciplines.
- Correlation of the simulation models with RTL, FPGA emulation, silicon.
- Scripting, automation of workflows, and verification methodologies.
Your responsibilities will include developing the SoC level solutions that drive the architecture of Apple’s future System-on-Chips. Your work will be highly visible and critical for delivering the best performance and power efficiency in Apple’s future products. You will be expected to collaborate with all the hardware and software teams that are part of Apple’s SoC development: - Develop memory models and run simulation experiments on various features to analyze performance and power. - Simulate and analyze the CPU, GPU, Camera, and Video data flows in our current products and drive modeling techniques for future products. - Collaborate with the power team to enable accurate system-level power estimation as well as independent power modeling. - Contribute to the specification of the future interconnection fabrics, QoS, system caches, and DRAM subsystems based on these findings. - Work with the multi-functional teams to develop architectural solutions. - Performance C++ modeling of proposed solutions. - Improve Apple’s modeling platform by developing APIs, tools, and best practice examples that can be used throughout the company. - Enable simulation of critical workloads at the “right” level of abstraction, to expertly deliver both performance and power estimates that can be trusted for SoC architecture decision-making. - Carefully analyze and present the system-level simulation results to enable data-driven architecture/design.
Education & Experience
MS or PhD in CS, EE, or related field.