Santa Clara Valley (Cupertino), California, United States
In this highly visible role, you will be a member of an performance model development effort interfacing with many disciplines, with a critical impact on future architectural performance, power, and area improvements.
- Strong problem solving and analytical skills
- Strong SW skills with good understanding of modular object oriented software development
- Knowledge of C/C++, Python, Lua, Perl preferred
- Model development and analysis experience preferred
- Outstanding written and verbal communications
- Excellent collaboration skills
- Proficiency in computer/SoC architecture and performance trade-offs
- Knowledge of Verilog and/or VHDL and experience with simulators and waveform debugging tools
- Ability to conduct experiments in all phases of design, gathering and analyzing data; and utilize scripting/spread sheet to document and present the results.
As a performance model developer for the IP blocks you will have responsibilities spanning all aspects of SOC performance, power, and area trade offs: • Working with architecture and design teams to plan and implement a high level performance model. The performance model is minimal feature set to meet the model requirements yet modular and flexible enough to be adapted for new projects and experiments. • Planning and analyzing results of performance studies for different micro-architectural proposals • Providing feedback to the architecture and design teams regarding the micro-architectural choices that may have been made. • Correlating performance model against the performance specifications, expectations, and help the verification team correlate against the RTL implementation.
Education & Experience
BS/MS in EE/CS is required 5 years of experience