Hardware, Silicon Technologies, ASIC Design Eng 3, CAD Engineer- Library & IP QA

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted: Nov 13, 2018
Role Number: 200011922
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a CAD engineer in the Library & IP QA group, you will be releasing groundbreaking technology Hard-IP, standard cell/io libraries, memory compilers and PDK releases. You will review and test IP materials to ensure high quality of deliverables to the entire design community. You will be exposed to many library views for different EDA tools as well as numerous design flows and technologies. Additional responsibilities include automation improvements of creation and release flows, communication with design teams to answer questions about the provided materials as well as driving issues to resolution with IP providers.

Key Qualifications

  • • Requires 3+ years of experience with EDA tools for IP development including digital and/or analog IP design and verification
  • • Scripting experience in Perl, Python or similar scripting language as well as be familiar with Unix level shell scripting, working knowledge of TCL a plus
  • • Previous experience using and modify “Makefiles” to build custom flows
  • • Experience with three or more of the following design view formats is required: Liberty view (i.e. *.lib/*.db), LEF/DEF views, Verilog/VHDL, CDL/Spice, SPEF and GDS
  • • Experience with the following leading commercial EDA tools is a bonus: Encounter/Innovus, IC Compiler II, Design Compiler, PrimeTime, Library Compiler, Verilog simulators (NC-Verilog, VCS, etc), DFT Tools (TetraMax, LBist, MBist, etc), view validation tools (Fractal – Crossfire, highly desirable) or characterization tools (Liberate, SiliconSmart, Zchar, etc)
  • • Knowledge of design flows including design verification, DFT, physical design & implementation is desirable.
  • • Strong communications skills; customer interfacing experience preferred

Description

In this role you will be: • Responsible for managing vendor IP/libraries and meeting quality metrics • Responsible for extensive use of Perl, Python, Shell Script and TCL languages to perform various flow automation duties  • Organize IP publishing statistics and QA results to ensure transparency • Work with a small team while chipping in to different CAD responsibilities

Education & Experience

BSEE/CE/CS or equivalent technical discipline, MSEE/CE/CS preferred

Additional Requirements