CAD Engineer- Library Characterization, Static Timing/Noise Analysis
Santa Clara Valley (Cupertino), California, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this hands-on role, you are responsible for defining, implementing, and supporting the methodologies, tools, and flows necessary to deliver high performance / low power standard cell designs, looking deep into the gate-level analysis down to transistors and semiconductor process. As a CAD engineer working on library characterization and static timing/noise analysis, you will work closely with teams of digital and analog designers to ensure that circuits meet functionality, timing, electrical, power and signal integrity goals for leading-edge silicon designs.
- You will have a mixture of academic and practical experience working in an area of circuit design, library development, characterization, design construction or static timing analysis. Strong interest in CAD tools, circuits, and spice simulation required.
- Library characterization experience with internal tools, Hspice, spectre or commercial tools such as Liberate, Variety, SiliconSmart, Liberty NCX.
- Experience with a variety of cell-level analysis tools like Primetime, Tempus, DC, ICC, Genus, Innovus, etc. is helpful.
- Stdcell library design and QA.
- Basic understanding of deep submicron process technologies and spice simulation.
- Good coding basics in Perl, Tcl, Python, C++ or other programming language(s).
- Detail oriented, tenacious and driven to take things apart and put them back together to understand how it all works.
-Define implement, and maintain cell characterization tools, flows, and QA. -Understand various downstream CAD tools and the standard methodologies in cell modeling to enable efficient and accurate design closure, front-end to back-end. -Support static timing glitch noise analysis and the associated spice-level stdcell characterization and correlation.
Education & Experience
BS or MS Degree in a technical discipline.