Power Grid Integrity Engineer
Santa Clara Valley (Cupertino), California, United States
As part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Join us, and you will help design products that bring to our customers experiences they’ve never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Power Grid Integrity Engineers. The SoC hardware development team is looking for motivated applicants to fill a full-time position. The primary role is to verify the integrity of the power grid. This includes setting the static IR drop and instantaneous voltage drop (IVD) targets for multiple SoCs and verifying that targets are met.
- We are looking for applicants with experience in ASIC design methodology with an emphasis on power grid
- Strong understanding of power grid integrity and reliability.
- Strong understanding of noise impact on circuit functionality and timing.
- Strong communication skills and ability to work on a team since the position requires collaborating with many
- different groups.
- Experience in spice simulations and library characterization.
- Experience in scripting.
- Good technical writing skills.
Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. The main responsibility of this role is to provide initial assessment of power grids for new chips and new technology, define settings for power grid simulations, and verify power grid integrity. You will be expected to: • Develop experimental flows for power integrity analysis tools using CAD flow - simulations include input from timing, package, and board level abstraction. • Drive initial assessment of static IR drop in power grids. • Drive initial assessment of IVD in power grids. • Drive initial assessment of power grid noise for jitter analysis. • Determine settings for SoC analysis for different type grids. • Determine settings for SoC for electro-migration/IR/IVD analysis. • Work with physical design and timing teams to analyze simulation results, verify that power grid integrity targets are met and enhance simulation flow. • Explore new tools and methodologies for power grid integrity.
Education & Experience
BS, MS, or Ph.D. in Computer Engineering, Electrical Engineering, or Computer Science.
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.