Hardware, Silicon Technologies, ASIC Design Eng 4, SR. CAD Timing Engineer

Santa Clara Valley (Cupertino), California, United States


Posted: Jan 3, 2019
Role Number: 200019339
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, a ​power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role as a senior level member of the Design Methodology and Tools team, you are an integral part of the effort to improve the performance of Apple silicon. You will be responsible for delivering industry-leading solutions for design optimization, design closure, and visualization. Combining algorithm application with practical design know-how and software engineering standard methodologies, you will help to differentiate and streamline Apple’s silicon engineering methods.

Key Qualifications

  • - Typically requires 8+ years of hands-on​ experience in static timing analysis and/or design optimization flows
  • - Familiar with STA of large high-performance SoC or Processor designs in deep sub-micron technologies
  • - Strong analytical skills and the ability to identify high-value opportunities
  • - Proficiency in optimization algorithms, data modeling, and mathematical representations
  • - Proven software engineering background and experience with C++, Python, Perl, Tcl programming languages and database technologies
  • - Deep understanding of cross-talk, variation, margins, and constraints
  • - A good communicator who can accurately assess, describe issues to management and follow solutions through to completion
  • - Familiarity with timing and power ECO techniques and implementation is a plus


As a Sr. CAD Timing Engineer, you will: - Deliver methodology and tool solutions for static timing closure and power optimization - Develop and apply a high performance, persistent design database with timing queries - Apply data science and ML analytics to quantify, mine, and predict intriguing patterns - Deploy innovative modeling and optimization solvers to achieve globally optimal targets - Prudently apply best-in-class algorithms for value-adding design solutions - Deep analysis of timing paths and power bottlenecks to isolate hands-on​ issues - Implement infrastructure to facilitate analytics and visualization - Partner with silicon design, CAD, and EDA partners to identify flow deficiencies and enact creative remedies

Education & Experience

BS, MS/PhD* preferred, a ​degree in technical field (*if fewer years of experience)

Additional Requirements