CAD Engineer - Front End Gate-Level Timing Flows & Methodologies
Santa Clara Valley (Cupertino), California, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this role on our team, you will be responsible for all aspects of Front End timing flows, working with design and integration teams on constraint generation/verification methodologies, and supporting the use of these constraints in various flows and tools.
- Typically requires 2+ years of experience in timing analysis flows and the following:
- Familiarity with the fundamentals of static timing analysis, with a deep understanding of constraints and timing intent
- Experience using EDA timing tools such as PrimeTime or Tempus a plus
- Prior hands-on experience in timing/SDC constraint generation is a plus
- Proficiency in analysis, tools, and methodologies for timing closure
- Understanding of programming fundamentals and concepts. Familiarity with Perl, Python, and/or Tcl is a plus
- Creative problem-solving skills
- Clear communicator who can accurately assess and describe issues to management and follow solutions through to completion
- Highly motivated go-getter with a strong technical curiosity
In this highly visible role you will: - Work with design teams to understand and debug issues related to timing constraints, including compatibility across various tools (STA, Synthesis, PNR, CDC, etc.) - Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best-practices across design teams - Develop and support tools for constraint generation and management for complex SOCs - Facilitate methodology changes to improve FE STA use case in the overall STA flow - Code and support various netlist quality checks - Provide user training on flows and conventions, document and help with guidelines/specs - Facilitate timing analysis handshaking between Front End and Physical Design engineering teams - Learn and deploy methods for mining and visualizing design timing progress and quality
Education & Experience
BS or MS degree in technical field.