SoC Physical Design Engineer, Electrical Analysis
Santa Clara Valley (Cupertino), California, United States
In this highly visible role, you will be responsible for the electrical analysis and verification of an SoC.
- Strong knowledge of analysis flows and methodology
- Knowledge of all aspects of ASIC physical design including floorplanning, clock and power distribution
- Familiarity with package modeling techniques for chip level power analysis
- Scripting skills to debug flow related issues and make enhancements as appropriate
- Experience in industry standard tools used for analysis such as Apache Redhawk, Voltagestorm, ETS, PT-SI, etc.
- Past experience of signoff on successful chip tapeouts
- Circuit design background and hspice experience a plus
As a member of the physical design team, you would be responsible for: • Performing various electrical analyses at the chip level, including but not limited to, Static/Dynamic IR, EM, Noise and Signal EM • Interface with the CAD/technology teams for flow bring up and validation • Working with the implementation team during the entire chip design cycle to drive signoff closure for tapeout • Managing schedules and supporting cross-functional engineering effort
Education & Experience
BSEE/MSEE is required.