Front-End Methodology CAD Engineer – Soft IP management, FE Infrastructure, RTL Automation & CI flow automation

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted: Dec 17, 2018
Role Number: 200021152
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role as a Front-End Methodology CAD engineer, you will play a major role in promoting a reliable work environment for Design and Design Verification (DV) teams. You will play a critical role where it allows the most concurrent development of IPs and fullchip integration within an SoC (system-on-chip) project. As the number of chips being designed concurrently increases, the need to develop IPs in a project agnostic environment while maintaining high standards is becoming a key aspect of chip design. In addition to maintaining and expanding this environment, you are responsible for working on a continuous integration (CI) system, such as TeamCity, and define automated workflows. Last but not least, you are required to learn the existing FE infrastructure and apply your knowledge to make the flows more robust.

Key Qualifications

  • Typically requires at least 3+ years of experience
  • Experience in a user-driven support role
  • Expertise PERL and/or Python is required
  • Experience with RTL build and run infrastructure
  • Experience in Verilog and System Verilog (and Verilog parsers) is a plus
  • Knowledge in Spyglass is a bonus
  • Deep understanding of FE design flow is a positive
  • Source control system management (Perforce) is a positive
  • Strong communication skills and prior experience in supporting VLSI flows
  • Relevant experience co-developing an existing, integrated debug system

Description

In this exciting role, you will: - Support and revamp, where necessary, existing soft IP methodology architecture - Define, implement, and support code management, build, test and check-in gatekeeper flows in the FE infrastructure - Identify, capture, and analyze metrics for improved automation reliability and hardware verification performance (Automation in a check-in gatekeeper need to be reliable, but fast with good coverage) - Work with TeamCity users across organization to build TeamCity plug-ins to standardize CI usage - Collaborate with design verification engineers across multiple design sites to understand requirements and deliver consistent and uniform solutions throughout the organization - Find opportunities for the development or deployment of new technologies and tools

Education & Experience

MS/BS Degree in a technical discipline

Additional Requirements