Santa Clara Valley (Cupertino), California, United States
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an ambitious and exceptionally talented Senior Clock Designer. As a member of our dynamic group, you will have the unique and rewarding opportunity to shape upcoming products that will delight and inspire millions of Apple’s customers every day. As a senior member of Apple’s clocking team, you will lead a small team of clock designers working on the latest technology nodes to create world-class clocking solutions for next generation SoC. This is a fast paced work environment with endless learning opportunities working within the design team with members of integration, CAD, circuit and technology engineering.
- - Typically requires 7+ years experience in clock distribution design of deep Sub-Micron technologies and CMOS circuits used in high performance SoCs
- - Prefer at least 5+ years experience in a lead capacity mentoring, overseeing and delegating work among clock designers
- - Experience in designing low skew, low power clock distribution networks and clock circuits
- - High-level proficiency in chip floor-planning, standard cell planning and hierarchical design assembly
- - Understand issues of RC delay, electro-migration, self-heating and cross capacitance
- - High-level proficiency in interpretation of extraction, h spice etc. reports
- - Knowledge of Spice and/or any fast simulator
- - Scripting skills in Matlab, PERL etc. are considered a plus, but not required
- - Excellent social skills and able to work with multi-functional teams
- - Clock Methodology for different types of blocks
- - Clock Skew Estimation and Budgeting
- - Clock Circuit Designs Clock Verification Requirements for CAD, PD etc.
- - Clock Verification and Sign-offs Working with various teams to understand the challenges and needs for clocks
- - Hands-on clock verification using spice
- - Knowledge in DDR PHY design, SerDes design techniques, PLL design
As a clock lead of the SoC, you will be responsible to lead clocking solutions for CPU, GPU, SOC, Analog, custom clocks. You will be responsible for crafting and developing clock distribution network for SoCs used in Apple mobile products.
Education & Experience
Bachelors or Masters Degree in Electrical Engineering preferred.