CAD Engineer- STA Methodology
Santa Clara Valley (Cupertino), California, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this multi-functional role, you will be working with CAD flow developers & design teams to develop timing closure methodology.
- We are looking for candidates with:
- 5+ years of relevant experience, including timing closure of gate level and transistor level designs in advanced CMOS process
- Deep knowledge of PrimeTime setup/flow automation, Spice simulation and understanding of derates and margins in typical STA/glitch noise closure is required for this role.
- A deep understanding of STA and methodologies for timing closure
- A deep understanding of noise, cross-talk, and OCV effects
- Excellent data analytical, problem solving, and interpersonal skills
- Ability to work with multi-functional teams and drive decision-making
- Prior experience delivering new designs to production under a very aggressive schedule
- Programming experience in Perl, Python or Tcl is a requirement
- Self-motivated and schedule oriented is a huge plus
In this exciting role, your responsibilities will include: - Driving STA and noise methodology working with Design, CAD and Technology teams - Working with the flow developers to incorporate timing closure requirements - Documenting and helping with guidelines/specs - Engaging parties in decision-making and working towards timely closure and thorough follow-through
Education & Experience
MS/BS in EE required