CPU Lead Physical Design Methodology Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intellectual people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver groundbreaking Apple products. In this role, you will be at the center of a processor design effort collaborating with architecture, CAD, timing, and logic design teams.
- You will have 10+ years of physical design experience on high performance CPU and/or SOC designs
- Knowledge of industry standards and practices in physical design, including physically aware synthesis and place & route
- Experience in developing and implementing power grid and clock specifications
- Working knowledge of computer architecture and HDL languages like Verilog
- Collaborate with logic design team for timing fixes
- Power user of industry standard physical design & synthesis tools
- Proven understanding of scripting languages such as Perl/Tcl
- Working knowledge of extraction and STA methodology tools
- Deep understanding of physical design verification methodology to debug LVS/DRC issues at block level
As a Lead Physical Design Methodology Engineer, you will be involved in all phases of physical design of high performance processors from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: • Generate Block/Chip level static timing constraints • Build block level floorplan including pin placement and power grid • Perform block level place and route and close the design to meet timing, area, and power constraints • Generate and implement ECOs to fix timing, noise and EM IR violations • Run physical design verification flow at block level and fix LVS/DRC violations • Participate in establishing CAD and physical design methodologies for correct by construction designs
Education & Experience
BS/MS/PhD CE, EE, or CS is required.