CPU Physical Electrical Analysis Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! As a CPU Physical Electrical Analysis Engineer, you will be driving the block and top level analysis of high performance processor projects in the EMIR/SIGEM/Reliability spheres.
- Background in electrical and computer engineering with experience and ability to understand design and architecture of high performance, low power designs and digital circuits as well as strong scripting and programming skills.
- Ability to write maintainable and reusable scripts/programs of medium complexity in suitable languages (Perl/Python/TCL/C++) to automate the efficient processing of large scale design and analysis data, debug issues, and isolate design sensitivities.
- Produce impactful design fixes and automate wherever possible, spanning multiple tool domains in physical construction and analysis.
- Good working knowledge of industry standard tools like Apache Redhawk, and Cadence Voltus as well as PNR implementation, layout tools, verification, and STA.
- In-depth knowledge in one or more of these tools is highly desired.
- Strong communication and presentation skills to regularly summarize the state of the design and drive design convergence across multiple blocks and teams in a timely fashion.
• Drive block and top-level EMIR/electrical verification closure. • Work on power grid design, construction, and implementation using existing infrastructures and where necessary, creating custom solutions in PNR tool environment. • Work multi-functionally with CAD/EDA vendors to ensure fidelity of analysis results; with methodology teams to cover unique use cases; with implementation to drive design and sign-off closure, and with the SOC level teams to meet IP delivery quality and schedule.
Education & Experience
BS/MSEE is required.